In an LED (light-emitting diode) array consisting of arranged light-emitting elements, bonding pads used for bonding wires to a driver circuit are provided. The bonding pads used for wire bonding require larger area than that of light-emitting elements. As the number of light-emitting elements per unit length is increased for a high-density image, the number of bonding pads is also increased. If the area of a bonding pad is not changed for a high-density image, a problem is caused such that the size of an LED array chip is enlarged because the area occupied by the pads is increased.
In order to resolve the problem, the inventor of the present application has interested in a three-terminal light-emitting thyristor having a pnpn-structure as an component of a light-emitting element array, and has already proposed a self-scanning light-emitting element array for realizing a self-scanning function of light-emitting points (see Japanese Patent Publications Nos. 1-238962, 2-14584, 2-92650, and 2-92651. These patent publications have disclosed that self-scanning light-emitting arrays may be easily mounted for an optical writing head of an optical printer, the array pitch of light-emitting elements may be fined, a compact self-scanning light-emitting element array may be fabricated, and so on.
FIG. 1 is a schematic cross-sectional view depicting a fundamental structure of a light-emitting thyristor. As shown in FIG. 1, on an n-type GaAs substrate 10 successively stacked are an n-type GaAs buffer layer 12, an n-type AlGaAs layer 14, a p-type AlGaAs layer 16, an n-type AlGaAs layer 18, and a p-type AlGaAs layer 20. On the AlGaAs layer 20 provided is an anode electrode 22, on the AlGaAs layer 18 a gate electrode 24, on the bottom surface of the GaAs substrate 10 a cathode electrode 26.
In this example, an n-type layer, a p-type layer, an n-type layer, and a p-type layer are stacked in this order on an n-type GaAs substrate via a buffer layer. However, a p-type layer, an n-type layer, a p-type layer, and an n-type layer may be stacked in this order on a p-type GaAs substrate via a buffer layer, in this case the uppermost electrode is a cathode one, and the bottommost electrode is an anode one.
Three fundamental structures of a self-scanning light-emitting array to which the light-emitting thyristor described above can be applied will now be described.
FIG. 2 shows an equivalent circuit diagram of a first fundamental structure of the self-scanning light-emitting array. According to the structure, light-emitting thyristors . . . T−2, T−1, T0, T+1, T+2 . . . are used as light-emitting elements, each of thyristors comprising gate electrodes . . . G−2, G−1, G0, G+1, G+2 . . . , respectively. Supply voltage VGK is applied to all of the gate electrodes via a load resistor RL, respectively. The neighboring gate electrodes are electrically connected to each other via a resistor RI to obtain interaction. Each of three transfer clock (φ1, φ2, φ3) lines 1, 2, 3 is connected to the anode electrode of each light-emitting thyristor at intervals of three elements (in a repeated manner).
The operation of this self-scanning light-emitting array will now be described. Assume that the transfer clock φ3 is at a high level, and the light-emitting thyristor T0 is turned on. At this time, the voltage of the gate electrode G0 is lowered to a level near zero volts due to the characteristic of the three-terminal light-emitting thyristor. Assuming that the supply voltage VGK is 5 volts, the gate voltage of each light-emitting thyristor is determined by the resistor network consisting of the load resistors RL and the interactive resistors RI. The gate voltage of a thyristor near the light-emitting thyristor T0 is lowered most, and the gate voltage of each subsequent thyristor rises as it is remote from the thyristor T0. This can be expressed as follows:VG0<VG+1=VG−1<VG+2=VG−2  (1)The difference among these voltages can be set by properly selecting the values of the load resistor RL and the interactive resistor RI.
It is known that the turn-on voltage VON of the three-terminal light-emitting thyristor is a voltage that is higher than the gate voltage by the diffusion potential Vdif as shown in the following formula.VON≈VG+Vdif  (2)Consequently, by setting the voltage applied to the anode to a level higher than this turn-on voltage VON, the light-emitting thyristor may be turned on.
In the state where the light-emitting thyristor T0 is turned on, the next transfer clock φ1 is raised to a high level voltage VH. Although this transfer clock φ1 is applied to the light-emitting thyristors T+1 and T−2 simultaneously, only the light-emitting thyristor T+1 can be turned on by setting the high-level voltage VH to the following range.VG−2+Vdif>VH>VG+1+Vdif  (3)
By doing this, the light-emitting thyristors T0 and T+1 are turned on simultaneously. When the transfer clock φ3 is lowered to a low level, the light-emitting thyristors T0 is turned off, and this completes transferring ON state.
In this manner, by connecting between the gate electrodes of each light-emitting thyristors with the resistor network in the self-scanning light-emitting element array, it is possible for a light-emitting thyristor to have a transfer function. Based on the principle described above, the ON state of the light-emitting thyristor is sequentially transferred by setting the high-level voltage of the transfer clocks φ1, φ2 and φ3 in such a manner as to overlap sequentially and slightly with each other, that is, the light-emitting point is sequentially transferred. In this way, the self-scanning light-emitting array according to the present invention is accomplished.
In this self-scanning light-emitting array chip, three bonding pads for transfer clock pulses φ1, φ2 and φ3, and one bonding pad for the supply voltage VGK are required per chip.
FIG. 3 shows an equivalent circuit diagram of a second fundamental structure of the self-scanning light-emitting array. This self-scanning light-emitting array uses a diode as means for electrically connecting the gate electrodes of light-emitting thyristors to each other. The light-emitting thyristors . . . T−2, T−1, T0, T+1, T+2 . . . are arrayed in one line, the gate electrodes thereof being designated by . . . G−2, G−1, G0, G+1, G+2 . . . . RL shows a load resistor for the gate electrode. The diodes to obtain electrical interaction are designated by . . . D−2, D−1, D0, D+1, D+2 . . . . VGK shows the supply voltage. Each of two transfer clock (φ1, φ2) lines 1, 2 is alternately connected to the anode electrode of each light-emitting thyristor.
The operation of this self-scanning light-emitting array will now be described. Assume that the transfer clock φ2 is at a high level, and the light-emitting thyristor T0 is turned on. At this time, the voltage of the gate electrode G0 is lowered to a level near zero volts due to the characteristic of the three-terminal light-emitting thyristor. Assuming that the supply voltage VGK is 5 volts, the gate voltage of each light-emitting thyristor is determined by the network consisting of the load resistors RL and the diodes . . . D−2, D−1, D0, D+1, D+2 . . . . The gate voltage of a thyristor near the light-emitting thyristor T0 is lowered most, and the gate voltage of each subsequent thyristor rises as it is remote from the thyristor T0.
The voltage reducing effect works only in the rightward direction from the light-emitting thyristor T0 due to the unidirectionality and asymmetry of diode characteristics. That is, the gate electrode G+1 is set at a higher voltage with respect to the gate electrode G0 by a forward rise voltage Vdif of the diode, while the gate electrode G+2 is set at a higher voltage with respect to the gate electrode G+1 by a forward rise voltage Vdif of the diode. On the other hand, current does not flow in the diode D−1 on the left side of the light-emitting thyristor T0 because the diode D−1 is reverse-viased. As a result, the gate electrode G−1 is at the same potential as the supply voltage VGK.
Although the next transfer clock φ1 is applied to the nearest light-emitting thyristor T+1, T−1; T+3, T−3; and so on, the thyristor having the lowest turn-on voltage among them is T+1, whose turn-on voltage is approximately the gate voltage of G+1+Vdif, about twice as high as Vdif. The thyristor having the second lowest turn-on voltage is T+3, about four times as high as Vdif. The turn-on voltage of the thyristors T−1 and T−3 is about VGK+Vdif.
It follows from the above discussion that by setting the high-level voltage of the transfer clock φ1 to a level about twice to four times as high as Vdif, only the light-emitting thyristor T+1 can be turned-on to perform a transfer operation.
In this self-scanning light-emitting element array, two bonding pads for the transfer clocks φ1 and φ2, and one bonding pad for the supply voltage VGK are required per chip.
FIG. 4 shows an equivalent circuit diagram of a third fundamental structure of the self-scanning light-emitting array. The light-emitting element array comprises switching elements . . . T−1, T0, T+1, T+2 . . . and writing light-emitting elements . . . L−1, L0, L+1, L+2 . . . . These switching elements and writing light-emitting elements consist of three-terminal light-emitting elements, respectively.
An example is shown in which a diode connection is used as the structure of a portion of switching elements. The gate . . . G−1, G0, G+1, . . . of the switching elements are connected to the gates of the writing light-emitting elements. A write signal Sin is applied to all of the anode of the writing light-emitting elements.
In the following, the operation of this self-scanning light-emitting array will be described. Assuming that the transfer element T0 is turned on, the voltage of the gate electrode G0 lowers below the supply voltage VGK (5 volts is assumed herein) and to almost zero volts. Consequently, if the voltage of the write signal Sin is higher than the diffusion potential (about 1 volt) of the pn junction, the light-emitting element L0 can be turned into a light-emission state.
On the other hand, the voltage of the gate electrode G−1 is about 5 volts, and the voltage of the gate electrode G+1 is about 1 volt. Consequently, the write voltage of the light-emitting element L−1 is about 6 volts, and the write voltage of the light-emitting element L+1 is about 2 volts. It follows from this that the voltage of the write signal Sin which can write only in the light-emitting element L0 is a range of about 1-2 volts. When the light-emitting element L0 is turned on, that is, in the light-emitting state, the voltage of the line 4 for the write signal Sin is fixed to about 1 volt. Thus, an error of selecting other light-emitting elements can be prevented.
Light emission intensity is determined by the amount of current fed to the write signal Sin, an image can be written at any desired intensity. In order to transfer the light-emitting state to the next light-emitting element, it is necessary to first turn off the element that is emitting light by temporarily reducing the voltage of the write signal Sin down to zero volts.
In this self-scanning light-emitting element array, three bonding pads φ1, φ2, φ3, one bonding pad for the supply voltage VGK, and one bonding pad for the write signal Sin are required per chip.
As described above, several bonding pads per chip may control many light-emitting points in the self-scanning light-emitting element array, so that it has a merit of almost no increasing of the number of bonding pads for even high-density image. It has also characteristic of being able to narrow the width of a chip (i.e., the length of a short side) for a high-density image by devising the arrangement of bonding pads in a chip, for example by locating bonding pads at the both ends of a chip, which is possible because the number of pads is originally less. Consequently, the number of chips acquired from one wafer may be increased so that a fabrication cost becomes low.
Where the width of a self-scanning light-emitting element array chip is lower than 0.2 mm, the problem is caused such that the chip is broken during the assembling of an optical writing head, because GaAs material used for a substrate of the chip is fragile, resulting in insufficient strength of the chip.